ISA Reference
Complete per-architecture instruction references for x86-64, AArch64, ARM32, Thumb and RISC-V, with operand forms and encoding notes.
Complete instruction references for each supported architecture.
Each reference page lists every supported instruction with its syntax, operand forms, and encoding notes. Click an architecture below to view its full reference.
| Architecture | Page | Scope |
|---|---|---|
| x86-64 | x86 / x86-64 | Data movement, ALU, SIMD (SSE–AVX-512), AES-NI, SHA, BMI, FMA, TSX |
| AArch64 | ARM64 / A64 | Data processing, shifted/extended operands, load/store, NEON/AdvSIMD, LSE atomics, SVE (opt-in) |
| ARM32 | ARMv7 / A32 | Data processing, barrel shifter, condition codes, load/store |
| Thumb | Thumb / T32 | 16-bit Thumb-1, 32-bit Thumb-2, IT blocks |
| RISC-V | RV32I / RV64I | Base ISA, M/A/F/D/V/C extensions |
Notation Conventions
All reference pages use a consistent notation:
| Symbol | Meaning |
|---|---|
r64 / r32 / r16 / r8 | Register of the specified bit width |
[mem] | Memory operand |
imm / #imm | Immediate value |
label | Label reference (resolved by the linker) |
cond | Condition code |
x86-64
x86 and x86-64 instruction reference: data movement, ALU, control flow, SSE through AVX-512, AES-NI, BMI and FMA.
AArch64
AArch64 (A64) instruction reference: data processing, shifted and extended operands, load/store, NEON/AdvSIMD and LSE atomics.
ARM32
ARM32 (A32) instruction reference: condition codes, the barrel shifter, register lists, load/store and literal pools.
Thumb
Thumb and Thumb-2 instruction reference: 16-bit and 32-bit encodings, IT blocks and automatic width selection.
RISC-V
RISC-V instruction reference: RV32I/RV64I base ISA plus the M, A, C, F/D and V extensions with automatic compression.